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HD74ALVCH162270
12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs
REJ03D0051-0300Z (Previous ADE-205-178A(Z)) Rev.3.00 Oct.02.2003
Description
The HD74ALVCH162270 is used in applications where data must be transferred from a narrow high speed bus to a wide lower frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low to high transition of the clock (CLK) input when the appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A to B direction, a two stage pipeline is provided in the A to 1B path, with a single storage register in the A to 2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active low output enables (OEA, OEB). The control terminals are registered to synchronize the bus direction changes with CLK. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 resistors to reduce overshoot and undershoot.
Features
* * * * * * VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) High output current 12 mA (@VCC = 3.0 V) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors All outputs have equivalent 26 series resistors, so no external resistors are required.
Rev.3.00, Oct.02.2003, page 1 of 12
HD74ALVCH162270
Function Table
Inputs CLK OEA H H L L OEB H L H L Outputs A Z Z Active Active 1B, 2B Z Active Z Active
Output enable
Inputs CLKENA1 X X L L H H H CLKENA2 H H L L L L H CLK X A L H L H L H X
Outputs 1B 1B0 1B0 L *2 H
*2 *1 *1 *1 *1, 2 *1, 2
2B 2B0 *1 2B0 *1 L H L H 2B0 *1
1B0 1B0 1B0
A- to-B storage (OEB = L)
Note: This functional table describes the case of transferring the same data for A to 1B path. For the case of transferring different data, see logic diagrams.
Inputs CLKEN1B H X L L X X CLKEN2B X H X X L L CLK X X SEL H L H H L L 1B X X L H X X 2B X X X X L H
Output A A0 *1 A0 *1 L H L H
B-to-A storage (OEA = L)
H : High level L : Low level X : Immaterial Z : High impedance : Low to high transition Notes: 1. Output level before the indicated steady state input conditions were established. 2. Two CLK edges are needed to propagate data.
Rev.3.00, Oct.02.2003, page 2 of 12
HD74ALVCH162270
Pin Arrangement
1OE 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 2Y1 8 2Y2 9 GND 10 2Y3 11 2Y4 12 3Y1 13 3Y2 14 GND 15 3Y3 16 3Y4 17 VCC 18 4Y1 19 4Y2 20 GND 21 4Y3 22 4Y4 23 4OE 24
48 2OE 47 1A1 46 1A2 45 GND 44 1A3 43 1A4 42 VCC 41 2A1 40 2A2 39 GND 38 2A3 37 2A4 36 3A1 35 3A2 34 GND 33 3A3 32 3A4 31 VCC 30 4A1 29 4A2 28 GND 27 4A3 26 4A4 25 3OE
(Top view)
Rev.3.00, Oct.02.2003, page 3 of 12
HD74ALVCH162270
Absolute Maximum Ratings
Item Supply voltage Input voltage
*1, 2
Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg
Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -50 50 50 100 1 -65 to 150
Unit V V V mA mA mA mA W C
Conditions Except I/O ports I/O ports VI < 0 VO < 0 or VO > VCC VO = 0 to VCC TSSOP
Output voltage
*1, 2
Input clamp current Output clamp current Continuous output current VCC, GND current / pin Maximum power dissipation *3 at Ta = 55C (in still air) Storage temperature
Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
Recommended Operating Conditions
Item Supply voltage Input voltage Output voltage High level output current Symbol VCC VI VO IOH Min 2.3 0 0 -- -- -- Low level output current IOL -- -- -- Input transition rise or fall rate Operating temperature t / v Ta 0 -40 Max 3.6 VCC VCC -6 -8 -12 6 8 12 10 85 ns / V C mA Unit V V V mA VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
Rev.3.00, Oct.02.2003, page 4 of 12
HD74ALVCH162270
Logic Diagram
CLK CLKEN1B CLKEN2B CLKENA1 CLKENA2 OEB SEL OEA
29 2 27 30 55
C1
56 28 1
1D
1D C1 G1 1 1 CE C1 1D
CE C1 1D CE C1 1D CE C1 1D CE C1 1D
1 of 12 Channels
23
1B1
A1
8
6
2B1
Rev.3.00, Oct.02.2003, page 5 of 12
HD74ALVCH162270
Electrical Characteristics
(Ta = -40 to 85C)
Item Input voltage Symbol VIH VIL Output voltage VOH VCC (V) Min Max -- -- 0.7 0.8 V IOH = -100 A IOH = -4 mA, VIH = 1.7 V IOH = -6 mA, VIH = 1.7 V IOH = -6 mA, VIH = 2.0 V IOH = -8 mA, VIH = 2.0 V IOH = -12 mA, VIH = 2.0 V IOL = 100 A IOL = 4 mA, VIL = 0.7 V IOL = 6 mA, VIL = 0.7 V IOL = 6 mA, VIL = 0.8 V IOL = 8 mA, VIL = 0.8 V IOL = 12 mA, VIL = 0.8 V A VIN = VCC or GND VIN = 0.7 V VIN = 1.7 V VIN = 0.8 V VIN = 2.0 V VIN = 0 to 3.6 V *1 A A VOUT = VCC or GND VIN = VCC or GND -- -- -- -- -- 0.2 0.4 0.55 0.55 0.6 0.8 5 -- -- -- -- 500 10 40 Unit Test Conditions V
2.3 to 2.7 1.7 2.7 to 3.6 2.0 2.3 to 2.7 -- 2.7 to 3.6 -- 2.3 2.3 3.0 2.7 3.0 1.9 1.7 2.4 2.0 2.0 -- -- -- -- -- -- 45 -45 75 -75 -- -- --
2.3 to 3.6 VCC-0.2 --
VOL
2.3 to 3.6 -- 2.3 2.3 3.0 2.7 3.0
Input current
IIN IIN (hold)
3.6 2.3 2.3 3.0 3.0 3.6
Off state output current Note:
IOZ
3.6 3.6
Quiescent supply current ICC
1. This is the bus hold maximum dynamic current required to switch the input from one state to another.
Rev.3.00, Oct.02.2003, page 6 of 12
HD74ALVCH162270
Switching Characteristics
(Ta = 0 to +70C)
Item Symbol VCC (V) Min Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.5 9.0 Max -- -- -- 6.9 6.4 5.6 6.4 6.0 5.2 7.2 7.0 6.0 7.9 7.4 6.5 7.8 7.1 6.2 -- -- pF pF Control inputs A or B ports ns CLK A or B ns CLK A or B SEL A CLK A ns CLK B Unit MHz FROM (Input) TO (Output)
Maximum clock frequency fmax
2.50.2 135 2.7 135 3.30.3 135
Propagation delay time
tPLH tPHL
2.50.2 2.5 2.7 -- 3.30.3 1.7 2.50.2 2.2 2.7 -- 3.30.3 1.6 2.50.2 2.4 2.7 -- 3.30.3 1.6
Output enable time
tZH tZL
2.50.2 2.1 2.7 -- 3.30.3 1.6
Output disable time
tHZ tLZ
2.50.2 3.0 2.7 3.3 3.3 -- -- -- 3.30.3 1.7
Input capacitance Output capacitance
CIN CIN / O
Rev.3.00, Oct.02.2003, page 7 of 12
HD74ALVCH162270
Switching Characteristics (cont.)
(Ta = -40 to 85C)
Item Setup time Symbol tsu VCC (V) 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Hold time th 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Pulse width tw 2.50.2 2.7 3.30.3 Min 4.1 3.8 3.1 0.9 1.2 0.9 3.5 3.2 2.7 3.4 3.0 2.6 4.4 3.9 3.2 0 0 0.2 1.4 1.0 1.7 0 0.1 0.3 0 0 0.6 0 0 0.1 3.3 3.3 3.3 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns CLK "H" or "L" OE after CLK CLKEN1B or CLKEN2B after CLK CLKENA1 or CLKENA2 after CLK B data after CLK ns A data after CLK OE before CLK CLKEN1B or CLKEN2B before CLK CLKENA1 or CLKENA2 before CLK B data before CLK Unit ns FROM (Input) A data before CLK
Rev.3.00, Oct.02.2003, page 8 of 12
HD74ALVCH162270
* Test Circuit
See under table 500 S1 OPEN
*1
GND 500
C L = 50 pF
Load Circuit for Outputs Symbol Vcc=2.50.2 V t PLH / t PHL OPEN t su / t h / t w t ZH/ t HZ t ZL / t LZ GND 4.6 V
Vcc = 2.7 V, 3.30.3 V
OPEN GND 6.0 V
Note: 1. C L includes probe and jig capacitance.
Rev.3.00, Oct.02.2003, page 9 of 12
HD74ALVCH162270
* Waveforms - 1
tr 90 % 90 % Vref
tf VIH 10 % t PLH t PHL GND
Input 10 %
Vref
VOH Output Vref Vref VOL
* Waveforms - 2
tr 90 % VIH GND VIH
Timing Input 10 % tsu
Vref th
Data Input
Vref
Vref GND tw VIH
Input
Vref
Vref GND
Rev.3.00, Oct.02.2003, page 10 of 12
HD74ALVCH162270
* Waveforms - 3
90 % Vref
tf
tr 90 % Vref 10 % t ZL Vref t ZH t HZ Vref VOH - 0.3 V 10 % t LZ GND VOH1 VIH
Output Control
Waveform - A
VOL + 0.3 V
VOL VOH VOL1
Waveform - B
TEST VIH Vref VOH1 VOL1
Vcc=2.50.2 V
Vcc=2.7 V, 3.30.3 V
2.3 V 1.2 V 2.3 V GND
2.7 V 1.5 V 3.0 V GND
Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50 , tr 2.5 ns, tf 2.5 ns. 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement.
Rev.3.00, Oct.02.2003, page 11 of 12
HD74ALVCH162270
Package Dimensions
As of January, 2003
14.0 14.2 Max 56 29 6.10
Unit: mm
1 *0.19 0.05
0.50 0.08 M
28
1.0 8.10 0.20 0 - 8 *0.15 0.05 0.10 0.05 0.50 0.1
0.65 Max
1.20 Max
0.10
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-56DAV -- -- 0.23 g
Rev.3.00, Oct.02.2003, page 12 of 12
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